This invention relates to sleep state transitioning.
To implement low power xe2x80x9csleepxe2x80x9d states in processor systems, INTEL(trademark) and others have proposed the Advanced Configuration and Power Interface Specification (xe2x80x9cACPIxe2x80x9d). ACPI defines an interface between the operating system and hardware that allows operating systems and hardware to interact, while permitting the design of operating systems and hardware to evolve independently. The description of the S1 and S2 sleep states found in the ACPI Specification, Revision 1.0b, released Feb. 2, 1999 is reproduced in an Appendix to this specification.
RAM subsystems can also have low power states. In some RAM subsystems, a memory controller communicates with the memory chips using a particular protocol. The memory controller is an intelligent device that is initialized before it begins the normal operation of reading data from and writing data to the memory chips. In the RDRAM(trademark) RAM subsystem, developed by RAMBUS(trademark), Inc. of Mountainview Calif. the memory controller includes a RAMBUS ASIC Cell (xe2x80x9cRACxe2x80x9d) that controls the electrical interface to the memory chips, performs multiplexing and demultiplexing functions, and converts data between a high speed proprietary serialized interface to the memory chips and the lower speed parallel interface used by the processor. The RDRAM subsystem can be powered down to conserve power. The RDRAM subsystem must be reinitialized after being powered down.
A system has a processor with multiple states, including an awake state and a sleep state, a memory subsystem including a memory controller and memory devices, and a second memory. The system uses software in the second memory to initialize the memory controller upon a transition from a sleep state to an awake state. The system detects a wake event trigger, and in response to the wake event trigger, executes software stored in the second memory to initialize the memory controller, and then executes software out of the first memory after the initialization.
In another aspect of the invention, the memory subsystem is RAM based and stores some or all of the operating system software. The software that initializes the memory controller is stored in the BIOS storage device. Prior to transitioning from an awake state to a sleep state, the operating system controls the preparation for the transition